This application claims priority to Korean Patent Application No. 2001-16065, filed on Mar. 27, 2001.
1. Technical Field
The present invention relates to a semiconductor memory device, and more particularly, to a semiconductor memory device that generates a high voltage using a reference voltage for a peripheral circuit and a voltage generating method thereof.
2. Description of Related Art
A conventional semiconductor memory device includes reference voltage generating circuits for a peripheral circuit and a memory cell array. In the conventional semiconductor memory device, the reference voltages for the peripheral circuit and the memory cell array are generated using a reference voltage that is generated in response to an external power voltage.
The reference voltage for the peripheral circuit is used for generating an internal power voltage for the peripheral circuit that is used in generating a high voltage and a substrate voltage. The reference voltage for the memory cell array is used for generating an internal power voltage, a substrate voltage and a bit line pre-charge voltage for the memory cell array. By using the two reference voltages for the peripheral circuit and the memory cell array, the conventional semiconductor memory device generates a plurality of direct-current voltages having a desired level therein. However, it is impossible to stably generate a plurality of the direct-current voltages having a desired level using the two reference voltages.
For example, a conventional semiconductor memory device generates a high voltage using an internal power voltage for a peripheral circuit but not an internal power voltage for a memory cell array. This is because the internal power voltage for the memory cell array is very noisy. Further, it is not easy to select a proper internal power voltage among a plurality of internal power voltages output from the memory cell array, because each bank in the memory cell array generates the internal power voltage to suppress a noise propagation using its internal power voltage generating circuit.
A conventional semiconductor memory device is designed to maintain a predetermined voltage difference between an internal power voltage for a memory cell array and a high voltage. If a voltage difference between the internal power voltage for the memory cell array and the high voltage is smaller than a desired voltage difference, a data transmission can be delayed when NMOS transistors transmit data having a logic xe2x80x9chighxe2x80x9d level.
However, since a conventional semiconductor memory device generates a high voltage using an internal power voltage for a peripheral circuit, a voltage difference between the internal power voltage for the peripheral circuit and the high voltage becomes smaller than a desired voltage difference, in response to a relatively low external power voltage. This is because the internal power voltage for the peripheral circuit is greater in level than the internal power voltage for the memory cell array. For example, when the relatively low external power voltage is applied to the device, the internal power voltage for the memory cell reaches a desired level faster than the internal power voltage for the peripheral circuit. The voltage difference between the high voltage and the internal power voltage for the memory cell array is decreased. As a result, a high voltage having a relatively low level is generated, thereby deteriorating an operation performance.
It is an object of the present invention to provide a semiconductor memory device that can stably generate a plurality of direct-current voltages having a desired level.
It is another object of the present invention to provide a semiconductor memory device having an excellent operation performance.
According to one aspect of the present invention, a semiconductor memory device comprises a plurality of direct-current voltage generating circuits for generating a plurality of direct-current voltages, and a plurality of reference voltage generating circuits for generating reference voltages for the plurality of the direct-current voltage generating circuits.
According to another aspect of the present invention, a semiconductor memory device comprises a memory cell array, a peripheral circuit for controlling a data transmission operation for the memory cell array, a first reference voltage generating circuit for generating a first reference voltage for the memory cell array in response to an external power voltage, a second reference voltage generating circuit for generating a second reference voltage for the peripheral circuit in response to the external power voltage, the second reference voltage being greater than the first reference voltage, a third reference voltage generating circuit for generating a third reference voltage for a high voltage in response to the external power voltage, and a high voltage generating circuit for generating the high voltage in response to the third reference voltage.
According to another aspect of the present invention, a semiconductor memory device comprises a memory cell array, a peripheral circuit for controlling a data transmission operation for the memory cell array, a first reference voltage generating circuit for generating a first reference voltage for the memory cell array in response to an external power voltage, a second reference voltage generating circuit for generating a second reference voltage for the peripheral circuit in response to the external power voltage, the second reference voltage being greater than the first reference voltage, and a high voltage generating circuit for receiving an external third reference voltage to generate a high voltage.
According to another aspect of the present invention, a method is provied for generating a voltage in a semiconductor memory device comprising the steps of generating a plurality of reference voltages for a plurality of direct-current circuits, in response to an external power voltage, and generating a plurality of direct-current voltages by the direct-current circuits in response to the plurality of the reference voltages.
According to another aspect of the present invention, a method is provided for generating a voltage in a semiconductor memory device comprising the stesp of generating first to third reference voltages in response to an external power voltage, wherein the first reference voltage is used for the memory cell array, wherein the second reference voltage is used for the peripheral circuit and is greater than first reference voltage, and wherein the third reference voltage is used for a high voltage, and generating the high voltage in response to the third reference voltage.
According to further aspect of the present invention, a method is provided for generating a voltage in a semiconductor memory device comprising the stesp of generating first and second reference voltages in response to an external power, the first reference voltage being for the memory cell array, the second reference voltage being for the peripheral circuit and greater than first reference voltage, and generating a high voltage in response to an external third reference voltage.
These and other aspects, factores, and advantages of the prosent invention will become apparent from the following detailed description of preferred embodiments, wihich is to be read in conujuction with the accompaning figures.